New CMOS Sensor Design and Compression Scheme
http://www.dpreview.com/news/0512/05121201new_chips.asp
A couple of professors at the University of Rochester in NY have developed some interesting technologies for future CMOS imaging devices:
* Extremely low power feedback design
* Increased dynamic range, by a factor of 100
* New compression scheme which utilizes a new pixel arrangement on the chip allows for a fraction of the processing power needed by current chips
We may be seeing 1/3″ and 2/3″ sensors having ISO1600 and above sensitivities with noise levels at that of current DSLR levels in the future.